188 lines
7.5 KiB
Python
188 lines
7.5 KiB
Python
# -*- coding: UTF-8 -*-
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import time
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from micropython import const
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_ES_MODULE_ADC = const(0x01)
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_ES_MODULE_DAC = const(0x02)
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_ES_MODULE_ADC_DAC = const(0x03)
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_ES_MODULE_LINE = const(0x04)
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_BIT_LENGTH_16BITS = const(0x03)
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_FMT_I2S_NORMAL = const(0x00)
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_I2S_MODE_SLAVE = const(0x00)
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_ADC_INPUT_LINE = const(0x01)
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_DAC_OUTPUT_ALL = const(0x02)
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_LCLK_DIV = const(256)
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_MCLK_DIV = const(0x04)
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class ES8374:
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def __init__(self, i2c_bus=None, i2c_addr=0x10, gain=5, pga_en=1):
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self.i2c_bus = i2c_bus
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self.i2c_addr = i2c_addr
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self.stop()
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self.init_reg(_I2S_MODE_SLAVE, ((_BIT_LENGTH_16BITS << 4) | _FMT_I2S_NORMAL), _DAC_OUTPUT_ALL, _ADC_INPUT_LINE)
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self.mic_gain(gain)
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self.pga_enable(pga_en)
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self.configI2SFormat(_ES_MODULE_ADC_DAC, _FMT_I2S_NORMAL)
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def _readReg(self, regAddr):
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return self.i2c_bus.readfrom_mem(self.i2c_addr, regAddr, 1)[0]
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def _writeReg(self, regAddr, data):
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self.i2c_bus.writeto_mem(self.i2c_addr, regAddr, data.to_bytes(1, 'little'))
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def init_reg(self, ms_mode, fmt, out_channel, in_channel):
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self._writeReg(0x00, 0x3F)# IC Rst start
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self._writeReg(0x00, 0x03)# IC Rst stop
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self._writeReg(0x01, 0x7F)# IC clk on # M ORG 7F
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self._writeReg(0x0f, (self._readReg(0x0F) & 0x7f) | (ms_mode << 7))# CODEC IN I2S SLAVE MODE
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self._writeReg(0x6F, 0xA0)# pll set:mode enable
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self._writeReg(0x72, 0x41)# pll set:mode set
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self._writeReg(0x09, 0x01)# pll set:reset on ,set start
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self._writeReg(0x0C, 0x22)# pll set:k
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self._writeReg(0x0D, 0x2E)# pll set:k
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self._writeReg(0x0E, 0xC6)# pll set:k
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self._writeReg(0x0A, 0x3A)# pll set:
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self._writeReg(0x0B, 0x07)# pll set:n
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self._writeReg(0x09, 0x41)# pll set:reset off ,set stop
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self.i2sConfigClock()
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self._writeReg(0x24, 0x08)# adc set
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self._writeReg(0x36, 0x00)# dac set
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self._writeReg(0x12, 0x30)# timming set
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self._writeReg(0x13, 0x20)# timming set
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self.configI2SFormat(_ES_MODULE_ADC, fmt)
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self.configI2SFormat(_ES_MODULE_DAC, fmt)
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self._writeReg(0x21, 0x50)# adc set: SEL LIN1 CH+PGAGAIN=0DB
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self._writeReg(0x22, 0xFF)# adc set: PGA GAIN=0DB
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self._writeReg(0x21, 0x14)# adc set: SEL LIN1 CH+PGAGAIN=18DB
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self._writeReg(0x22, 0x55)# pga = +15db
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self._writeReg(0x08, 0x21)# set class d divider = 33, to avoid the high frequency tone on laudspeaker
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self._writeReg(0x00, 0x80)# IC START
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time.sleep(0.05)
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self._writeReg(0x25, 0x00)# ADCVOLUME on
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self._writeReg(0x38, 0x00)# DACVOLUME on
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self._writeReg(0x14, 0x8A)# IC START
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self._writeReg(0x15, 0x40)# IC START
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self._writeReg(0x1A, 0xA0)# monoout set
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self._writeReg(0x1B, 0x19)# monoout set
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self._writeReg(0x1C, 0x90)# spk set
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self._writeReg(0x1D, 0x01)# spk set
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self._writeReg(0x1F, 0x00)# spk set
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self._writeReg(0x1E, 0x20)# spk on
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self._writeReg(0x28, 0x70)# alc set 0x70
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#self._writeReg(0x26, 0x4E)# alc set
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#self._writeReg(0x27, 0x10)# alc set
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#self._writeReg(0x29, 0x00)# alc set
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#self._writeReg(0x2B, 0x00)# alc set
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self._writeReg(0x25, 0x00)# ADCVOLUME on
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self._writeReg(0x38, 0x00)# DACVOLUME on
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self._writeReg(0x37, 0x30)# dac set
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self._writeReg(0x6D, 0x60)# SEL:GPIO1=DMIC CLK OUT+SEL:GPIO2=PLL CLK OUT
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self._writeReg(0x71, 0x05)# for automute setting
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self._writeReg(0x73, 0x70)
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self.configDACOutput(out_channel)# 0x3c Enable DAC and Enable Lout/Rout/1/2
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self.configADCInput(in_channel)# 0x00 LINSEL & RINSEL, LIN1/RIN1 as ADC Input DSSEL,use one DS Reg11 DSR, LINPUT1-RINPUT1
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self.voice_volume(95)
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self._writeReg(0x37, 0x00)# dac set
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'''
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reg = self._readReg(0x1a) # disable lout
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reg |= 0x08
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self._writeReg(0x1a, reg)
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reg &= 0xdf
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self._writeReg(0x1a, reg)
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self._writeReg(0x1D, 0x12) # mute speaker
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self._writeReg(0x1E, 0x20) # disable class d
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reg = self._readReg(0x15) # power up dac
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reg &= 0xdf
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self._writeReg(0x15, reg)
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reg = self._readReg(0x1a) # disable lout
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reg |= 0x20
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self._writeReg(0x1a, reg)
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reg &= 0xf7
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self._writeReg(0x1a, reg)
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self._writeReg(0x1D, 0x02) # mute speaker
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self._writeReg(0x1E, 0xa0) # disable class d
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self.voice_mute(0)
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'''
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def stop(self):
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self.voice_mute(1)
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self._writeReg(0x1a, self._readReg(0x1a)| 0x08)
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self._writeReg(0x1a, self._readReg(0x1a)& 0xdf)
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self._writeReg(0x1D, 0x12)# mute speaker
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self._writeReg(0x1E, 0x20)# disable class d
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self._writeReg(0x15, self._readReg(0x15)| 0x20)
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self._writeReg(0x10, self._readReg(0x10)| 0xc0)
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self._writeReg(0x21, self._readReg(0x21)| 0xc0)
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def i2sConfigClock(self):
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self._writeReg(0x0f, (self._readReg(0x0F) & 0xe0) | _MCLK_DIV)
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self._writeReg(0x06, _LCLK_DIV >> 8)# ADCFsMode,singel SPEED,RATIO=256
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self._writeReg(0x07, _LCLK_DIV & 0xFF)# ADCFsMode,singel SPEED,RATIO=256
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def configI2SFormat(self, mode, fmt):
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fmt_tmp = ((fmt & 0xf0) >> 4)
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fmt_i2s = fmt & 0x0f
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if (mode == _ES_MODULE_ADC or mode == _ES_MODULE_ADC_DAC):
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reg = self._readReg(0x10)
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reg &= 0xfc
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self._writeReg(0x10, (reg|fmt_i2s))
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self.setBitsPerSample(mode, 3)
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if (mode == _ES_MODULE_DAC or mode == _ES_MODULE_ADC_DAC):
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reg = self._readReg(0x11)
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reg &= 0xfc
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self._writeReg(0x11, (reg|fmt_i2s))
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self.setBitsPerSample(mode, 3)
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# set Bits Per Sample
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def setBitsPerSample(self, mode, bit_per_smaple):
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bits = bit_per_smaple & 0x0f
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if (mode == _ES_MODULE_ADC or mode == _ES_MODULE_ADC_DAC):
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reg = self._readReg(0x10)
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reg &= 0xe3
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self._writeReg(0x10, (reg| (bits << 2)))
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if (mode == _ES_MODULE_DAC or mode == _ES_MODULE_ADC_DAC):
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reg = self._readReg(0x11)
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reg &= 0xe3
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self._writeReg(0x11, (reg| (bits << 2)))
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def configDACOutput(self, output):
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self._writeReg(0x1d, 0x02)
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reg = self._readReg(0x1c) # set spk mixer
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reg |= 0x80
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self._writeReg(0x1c, reg)
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self._writeReg(0x1D, 0x02) # spk set
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self._writeReg(0x1F, 0x00) # spk set
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self._writeReg(0x1E, 0xA0) # spk on
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def configADCInput(self, input):
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reg = self._readReg(0x21)
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reg = (reg & 0xcf) | 0x24
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self._writeReg( 0x21, reg)
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def mic_volume(self, volume=None):
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if volume is None:
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return round(100 - self._readReg(0x25) * 100 / 192)
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else:
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self._writeReg(0x25, (100 - volume) * 192 // 100)
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def voice_volume(self, volume=None):
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if volume is None:
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return round(100 - self._readReg(0x38) * 100 / 192)
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else:
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self._writeReg(0x38, (100 - volume) * 192 // 100)
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def voice_mute(self, enable=None):
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if enable is None:
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return True if self._readReg(0x36) & 0x40 else False
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else:
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self._writeReg(0x36, (self._readReg(0x36)& 0xdf) | (enable << 5))
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def mic_gain(self, gain):
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gain_n = max(min(gain, 15), 0)
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self._writeReg(0x22, (gain_n | (gain_n<<4))) # MIC PGA -3.5db ~ 24db
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def pga_enable(self, enable):
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self._writeReg(0x21, (self._readReg(0x21) & 0xfb) | (enable << 2)) # MIC PGA 0db or 15db
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