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feat(core): 更新py-esptool (version: 4.8.1)

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This commit is contained in:
王立帮
2025-04-07 23:51:29 +08:00
parent 6b4ca0a883
commit 937ecf44f4
120 changed files with 1871 additions and 8899 deletions
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6
tools/python/esptool/targets/__init__.py
View File

@@ -1,7 +1,10 @@
from .esp32 import ESP32ROM
from .esp32c2 import ESP32C2ROM
from .esp32c3 import ESP32C3ROM
from .esp32c5 import ESP32C5ROM
from .esp32c5beta3 import ESP32C5BETA3ROM
from .esp32c6 import ESP32C6ROM
from .esp32c61 import ESP32C61ROM
from .esp32c6beta import ESP32C6BETAROM
from .esp32h2 import ESP32H2ROM
from .esp32h2beta1 import ESP32H2BETA1ROM
@@ -25,6 +28,9 @@ CHIP_DEFS = {
"esp32h2beta2": ESP32H2BETA2ROM,
"esp32c2": ESP32C2ROM,
"esp32c6": ESP32C6ROM,
"esp32c61": ESP32C61ROM,
"esp32c5": ESP32C5ROM,
"esp32c5beta3": ESP32C5BETA3ROM,
"esp32h2": ESP32H2ROM,
"esp32p4": ESP32P4ROM,
}

138
tools/python/esptool/targets/esp32.py
View File

@@ -5,9 +5,10 @@
import struct
import time
from typing import Dict, Optional
from loader import ESPLoader
from util import FatalError, NotSupportedError
from ..loader import ESPLoader
from ..util import FatalError, NotSupportedError
class ESP32ROM(ESPLoader):
@@ -36,6 +37,9 @@ class ESP32ROM(ESPLoader):
SPI_MISO_DLEN_OFFS = 0x2C
EFUSE_RD_REG_BASE = 0x3FF5A000
EFUSE_BLK0_RDATA3_REG_OFFS = EFUSE_RD_REG_BASE + 0x00C
EFUSE_BLK0_RDATA5_REG_OFFS = EFUSE_RD_REG_BASE + 0x014
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE + 0x18
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 7 # EFUSE_RD_DISABLE_DL_ENCRYPT
@@ -46,6 +50,11 @@ class ESP32ROM(ESPLoader):
EFUSE_RD_ABS_DONE_0_MASK = 1 << 4
EFUSE_RD_ABS_DONE_1_MASK = 1 << 5
EFUSE_VDD_SPI_REG = EFUSE_RD_REG_BASE + 0x10
VDD_SPI_XPD = 1 << 14 # XPD_SDIO_REG
VDD_SPI_TIEH = 1 << 15 # XPD_SDIO_TIEH
VDD_SPI_FORCE = 1 << 16 # XPD_SDIO_FORCE
DR_REG_SYSCON_BASE = 0x3FF66000
APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C
APB_CTL_DATE_V = 0x1
@@ -61,6 +70,17 @@ class ESP32ROM(ESPLoader):
TIMERS_RTC_CALI_VALUE = 0x01FFFFFF
TIMERS_RTC_CALI_VALUE_S = 7
GPIO_STRAP_REG = 0x3FF44038
GPIO_STRAP_VDDSPI_MASK = 1 << 5 # GPIO_STRAP_VDDSDIO
RTC_CNTL_SDIO_CONF_REG = 0x3FF48074
RTC_CNTL_XPD_SDIO_REG = 1 << 31
RTC_CNTL_DREFH_SDIO_M = 3 << 29
RTC_CNTL_DREFM_SDIO_M = 3 << 27
RTC_CNTL_DREFL_SDIO_M = 3 << 25
RTC_CNTL_SDIO_FORCE = 1 << 22
RTC_CNTL_SDIO_PD_EN = 1 << 21
FLASH_SIZES = {
"1MB": 0x00,
"2MB": 0x10,
@@ -105,6 +125,8 @@ class ESP32ROM(ESPLoader):
UF2_FAMILY_ID = 0x1C5F21B0
KEY_PURPOSES: Dict[int, str] = {}
""" Try to read the BLOCK1 (encryption key) and check if it is valid """
def is_flash_encryption_key_valid(self):
@@ -121,7 +143,7 @@ class ESP32ROM(ESPLoader):
# When ESP32 has not generated AES/encryption key in BLOCK1,
# the contents will be readable and 0.
# If the flash encryption is enabled it is expected to have a valid
# non-zero key. We break out on first occurance of non-zero value
# non-zero key. We break out on first occurrence of non-zero value
key_word = [0] * 7
for i in range(len(key_word)):
key_word[i] = self.read_efuse(14 + i)
@@ -205,11 +227,11 @@ class ESP32ROM(ESPLoader):
major_rev = self.get_major_chip_version()
minor_rev = self.get_minor_chip_version()
rev3 = major_rev == 3
single_core = self.read_efuse(3) & (1 << 0) # CHIP_VER DIS_APP_CPU
sc = self.read_efuse(3) & (1 << 0) # single core, CHIP_VER DIS_APP_CPU
chip_name = {
0: "ESP32-S0WDQ6" if single_core else "ESP32-D0WDQ6",
1: "ESP32-S0WD" if single_core else "ESP32-D0WD",
0: "ESP32-S0WDQ6" if sc else "ESP32-D0WDQ6-V3" if rev3 else "ESP32-D0WDQ6",
1: "ESP32-S0WD" if sc else "ESP32-D0WD-V3" if rev3 else "ESP32-D0WD",
2: "ESP32-D2WD",
4: "ESP32-U4WDH",
5: "ESP32-PICO-V3" if rev3 else "ESP32-PICO-D4",
@@ -217,10 +239,6 @@ class ESP32ROM(ESPLoader):
7: "ESP32-D0WDR2-V3",
}.get(pkg_version, "unknown ESP32")
# ESP32-D0WD-V3, ESP32-D0WDQ6-V3
if chip_name.startswith("ESP32-D0WD") and rev3:
chip_name += "-V3"
return f"{chip_name} (revision v{major_rev}.{minor_rev})"
def get_chip_features(self):
@@ -269,13 +287,30 @@ class ESP32ROM(ESPLoader):
coding_scheme = word6 & 0x3
features += [
"Coding Scheme %s"
% {0: "None", 1: "3/4", 2: "Repeat (UNSUPPORTED)", 3: "Invalid"}[
coding_scheme
]
% {
0: "None",
1: "3/4",
2: "Repeat (UNSUPPORTED)",
3: "None (may contain encoding data)",
}[coding_scheme]
]
return features
def get_chip_spi_pads(self):
"""Read chip spi pad config
return: clk, q, d, hd, cd
"""
efuse_blk0_rdata5 = self.read_reg(self.EFUSE_BLK0_RDATA5_REG_OFFS)
spi_pad_clk = efuse_blk0_rdata5 & 0x1F
spi_pad_q = (efuse_blk0_rdata5 >> 5) & 0x1F
spi_pad_d = (efuse_blk0_rdata5 >> 10) & 0x1F
spi_pad_cs = (efuse_blk0_rdata5 >> 15) & 0x1F
efuse_blk0_rdata3_reg = self.read_reg(self.EFUSE_BLK0_RDATA3_REG_OFFS)
spi_pad_hd = (efuse_blk0_rdata3_reg >> 4) & 0x1F
return spi_pad_clk, spi_pad_q, spi_pad_d, spi_pad_hd, spi_pad_cs
def read_efuse(self, n):
"""Read the nth word of the ESP3x EFUSE region."""
return self.read_reg(self.EFUSE_RD_REG_BASE + (4 * n))
@@ -295,32 +330,63 @@ class ESP32ROM(ESPLoader):
def get_erase_size(self, offset, size):
return size
def _get_efuse_flash_voltage(self) -> Optional[str]:
efuse = self.read_reg(self.EFUSE_VDD_SPI_REG)
# check efuse setting
if efuse & (self.VDD_SPI_FORCE | self.VDD_SPI_XPD | self.VDD_SPI_TIEH):
return "3.3V"
elif efuse & (self.VDD_SPI_FORCE | self.VDD_SPI_XPD):
return "1.8V"
elif efuse & self.VDD_SPI_FORCE:
return "OFF"
return None
def _get_rtc_cntl_flash_voltage(self) -> Optional[str]:
reg = self.read_reg(self.RTC_CNTL_SDIO_CONF_REG)
# check if override is set in RTC_CNTL_SDIO_CONF_REG
if reg & self.RTC_CNTL_SDIO_FORCE:
if reg & self.RTC_CNTL_DREFH_SDIO_M:
return "1.9V"
elif reg & self.RTC_CNTL_XPD_SDIO_REG:
return "1.8V"
else:
return "OFF"
return None
def get_flash_voltage(self):
"""Get flash voltage setting and print it to the console."""
voltage = self._get_rtc_cntl_flash_voltage()
source = "RTC_CNTL"
if not voltage:
voltage = self._get_efuse_flash_voltage()
source = "eFuse"
if not voltage:
strap_reg = self.read_reg(self.GPIO_STRAP_REG)
strap_reg &= self.GPIO_STRAP_VDDSPI_MASK
voltage = "1.8V" if strap_reg else "3.3V"
source = "a strapping pin"
print(f"Flash voltage set by {source} to {voltage}")
def override_vddsdio(self, new_voltage):
new_voltage = new_voltage.upper()
if new_voltage not in self.OVERRIDE_VDDSDIO_CHOICES:
raise FatalError(
"The only accepted VDDSDIO overrides are '1.8V', '1.9V' and 'OFF'"
f"The only accepted VDDSDIO overrides are {', '.join(self.OVERRIDE_VDDSDIO_CHOICES)}"
)
RTC_CNTL_SDIO_CONF_REG = 0x3FF48074
RTC_CNTL_XPD_SDIO_REG = 1 << 31
RTC_CNTL_DREFH_SDIO_M = 3 << 29
RTC_CNTL_DREFM_SDIO_M = 3 << 27
RTC_CNTL_DREFL_SDIO_M = 3 << 25
# RTC_CNTL_SDIO_TIEH = (1 << 23)
# not used here, setting TIEH=1 would set 3.3V output,
# RTC_CNTL_SDIO_TIEH is not used here, setting TIEH=1 would set 3.3V output,
# not safe for esptool.py to do
RTC_CNTL_SDIO_FORCE = 1 << 22
RTC_CNTL_SDIO_PD_EN = 1 << 21
reg_val = RTC_CNTL_SDIO_FORCE # override efuse setting
reg_val |= RTC_CNTL_SDIO_PD_EN
reg_val = self.RTC_CNTL_SDIO_FORCE # override efuse setting
reg_val |= self.RTC_CNTL_SDIO_PD_EN
if new_voltage != "OFF":
reg_val |= RTC_CNTL_XPD_SDIO_REG # enable internal LDO
reg_val |= self.RTC_CNTL_XPD_SDIO_REG # enable internal LDO
if new_voltage == "1.9V":
reg_val |= (
RTC_CNTL_DREFH_SDIO_M | RTC_CNTL_DREFM_SDIO_M | RTC_CNTL_DREFL_SDIO_M
self.RTC_CNTL_DREFH_SDIO_M
| self.RTC_CNTL_DREFM_SDIO_M
| self.RTC_CNTL_DREFL_SDIO_M
) # boost voltage
self.write_reg(RTC_CNTL_SDIO_CONF_REG, reg_val)
self.write_reg(self.RTC_CNTL_SDIO_CONF_REG, reg_val)
print("VDDSDIO regulator set to %s" % new_voltage)
def read_flash_slow(self, offset, length, progress_fn):
@@ -329,11 +395,17 @@ class ESP32ROM(ESPLoader):
data = b""
while len(data) < length:
block_len = min(BLOCK_LEN, length - len(data))
r = self.check_command(
"read flash block",
self.ESP_READ_FLASH_SLOW,
struct.pack("<II", offset + len(data), block_len),
)
try:
r = self.check_command(
"read flash block",
self.ESP_READ_FLASH_SLOW,
struct.pack("<II", offset + len(data), block_len),
)
except FatalError:
print(
"Hint: Consider specifying flash size using '--flash_size' argument"
)
raise
if len(r) < block_len:
raise FatalError(
"Expected %d byte block, got %d bytes. Serial errors?"

13
tools/python/esptool/targets/esp32c2.py
View File

@@ -5,10 +5,11 @@
import struct
import time
from typing import Dict
from .esp32c3 import ESP32C3ROM
from loader import ESPLoader
from util import FatalError
from ..loader import ESPLoader
from ..util import FatalError
class ESP32C2ROM(ESP32C3ROM):
@@ -20,8 +21,8 @@ class ESP32C2ROM(ESP32C3ROM):
DROM_MAP_START = 0x3C000000
DROM_MAP_END = 0x3C400000
# Magic value for ESP32C2 ECO0 and ECO1 respectively
CHIP_DETECT_MAGIC_VALUE = [0x6F51306F, 0x7C41A06F]
# Magic value for ESP32C2 ECO0 , ECO1 and ECO4 respectively
CHIP_DETECT_MAGIC_VALUE = [0x6F51306F, 0x7C41A06F, 0x0C21E06F]
EFUSE_BASE = 0x60008800
EFUSE_BLOCK2_ADDR = EFUSE_BASE + 0x040
@@ -64,6 +65,8 @@ class ESP32C2ROM(ESP32C3ROM):
UF2_FAMILY_ID = 0x2B88D29C
KEY_PURPOSES: Dict[int, str] = {}
def get_pkg_version(self):
num_word = 1
return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 22) & 0x07
@@ -146,7 +149,7 @@ class ESP32C2ROM(ESP32C3ROM):
# When chip has not generated AES/encryption key in BLOCK3,
# the contents will be readable and 0.
# If the flash encryption is enabled it is expected to have a valid
# non-zero key. We break out on first occurance of non-zero value
# non-zero key. We break out on first occurrence of non-zero value
key_word = [0] * 7 if key_len_256 else [0] * 3
for i in range(len(key_word)):
key_word[i] = self.read_reg(self.EFUSE_BLOCK_KEY0_REG + i * 4)

34
tools/python/esptool/targets/esp32c3.py
View File

@@ -4,10 +4,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from typing import Dict
from .esp32 import ESP32ROM
from loader import ESPLoader
from util import FatalError, NotImplementedInROMError
from ..loader import ESPLoader
from ..util import FatalError, NotImplementedInROMError
class ESP32C3ROM(ESP32ROM):
@@ -27,6 +28,8 @@ class ESP32C3ROM(ESP32ROM):
SPI_MISO_DLEN_OFFS = 0x28
SPI_W0_OFFS = 0x58
SPI_ADDR_REG_MSB = False
BOOTLOADER_FLASH_OFFSET = 0x0
# Magic values for ESP32-C3 eco 1+2, eco 3, eco 6, and eco 7 respectively
@@ -99,6 +102,20 @@ class ESP32C3ROM(ESP32ROM):
UF2_FAMILY_ID = 0xD42BA06C
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "RESERVED",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
}
def get_pkg_version(self):
num_word = 3
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07
@@ -152,6 +169,9 @@ class ESP32C3ROM(ESP32ROM):
# ESP32C3 XTAL is fixed to 40MHz
return 40
def get_flash_voltage(self):
pass # not supported on ESP32-C3
def override_vddsdio(self, new_voltage):
raise NotImplementedInROMError(
"VDD_SDIO overrides are not supported for ESP32-C3"
@@ -176,8 +196,10 @@ class ESP32C3ROM(ESP32ROM):
)
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -191,7 +213,9 @@ class ESP32C3ROM(ESP32ROM):
def is_flash_encryption_key_valid(self):
# Need to see an AES-128 key
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)

190
tools/python/esptool/targets/esp32c5.py Normal file
View File

@@ -0,0 +1,190 @@
# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
import time
from typing import Dict
from .esp32c6 import ESP32C6ROM
from ..loader import ESPLoader
from ..reset import HardReset
from ..util import FatalError
class ESP32C5ROM(ESP32C6ROM):
CHIP_NAME = "ESP32-C5"
IMAGE_CHIP_ID = 23
EFUSE_BASE = 0x600B4800
EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
MAC_EFUSE_REG = EFUSE_BASE + 0x044
EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address
EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY0_SHIFT = 24
EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY1_SHIFT = 28
EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
EFUSE_PURPOSE_KEY2_SHIFT = 0
EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
EFUSE_PURPOSE_KEY3_SHIFT = 4
EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
EFUSE_PURPOSE_KEY4_SHIFT = 8
EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
EFUSE_PURPOSE_KEY5_SHIFT = 12
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
IROM_MAP_START = 0x42000000
IROM_MAP_END = 0x42800000
DROM_MAP_START = 0x42800000
DROM_MAP_END = 0x43000000
PCR_SYSCLK_CONF_REG = 0x60096110
PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24
PCR_SYSCLK_XTAL_FREQ_S = 24
UARTDEV_BUF_NO = 0x4085F51C # Variable in ROM .bss which indicates the port in use
# Magic value for ESP32C5
CHIP_DETECT_MAGIC_VALUE = [0x1101406F]
FLASH_FREQUENCY = {
"80m": 0xF,
"40m": 0x0,
"20m": 0x2,
}
MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x42800000, 0x43000000, "DROM"],
[0x40800000, 0x40860000, "DRAM"],
[0x40800000, 0x40860000, "BYTE_ACCESSIBLE"],
[0x4003A000, 0x40040000, "DROM_MASK"],
[0x40000000, 0x4003A000, "IROM_MASK"],
[0x42000000, 0x42800000, "IROM"],
[0x40800000, 0x40860000, "IRAM"],
[0x50000000, 0x50004000, "RTC_IRAM"],
[0x50000000, 0x50004000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
]
UF2_FAMILY_ID = 0xF71C0343
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
12: "KM_INIT_KEY",
}
def get_pkg_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 26) & 0x07
def get_minor_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
def get_major_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03
def get_chip_description(self):
chip_name = {
0: "ESP32-C5",
}.get(self.get_pkg_version(), "unknown ESP32-C5")
major_rev = self.get_major_chip_version()
minor_rev = self.get_minor_chip_version()
return f"{chip_name} (revision v{major_rev}.{minor_rev})"
def get_crystal_freq(self):
# The crystal detection algorithm of ESP32/ESP8266
# works for ESP32-C5 as well.
return ESPLoader.get_crystal_freq(self)
def get_crystal_freq_rom_expect(self):
return (
self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V
) >> self.PCR_SYSCLK_XTAL_FREQ_S
def hard_reset(self):
print("Hard resetting via RTS pin...")
HardReset(self._port, self.uses_usb_jtag_serial())()
def change_baud(self, baud):
if not self.IS_STUB:
crystal_freq_rom_expect = self.get_crystal_freq_rom_expect()
crystal_freq_detect = self.get_crystal_freq()
print(
f"ROM expects crystal freq: {crystal_freq_rom_expect} MHz, detected {crystal_freq_detect} MHz"
)
baud_rate = baud
# If detect the XTAL is 48MHz, but the ROM code expects it to be 40MHz
if crystal_freq_detect == 48 and crystal_freq_rom_expect == 40:
baud_rate = baud * 40 // 48
# If detect the XTAL is 40MHz, but the ROM code expects it to be 48MHz
elif crystal_freq_detect == 40 and crystal_freq_rom_expect == 48:
baud_rate = baud * 48 // 40
else:
ESPLoader.change_baud(self, baud_rate)
return
print(f"Changing baud rate to {baud_rate}")
self.command(self.ESP_CHANGE_BAUDRATE, struct.pack("<II", baud_rate, 0))
print("Changed.")
self._set_port_baudrate(baud)
time.sleep(0.05) # get rid of garbage sent during baud rate change
self.flush_input()
else:
ESPLoader.change_baud(self, baud)
def check_spi_connection(self, spi_connection):
if not set(spi_connection).issubset(set(range(0, 29))):
raise FatalError("SPI Pin numbers must be in the range 0-28.")
if any([v for v in spi_connection if v in [13, 14]]):
print(
"WARNING: GPIO pins 13 and 14 are used by USB-Serial/JTAG, "
"consider using other pins for SPI flash connection."
)
class ESP32C5StubLoader(ESP32C5ROM):
"""Access class for ESP32C5 stub loader, runs on top of ROM.
(Basically the same as ESP32StubLoader, but different base class.
Can possibly be made into a mixin.)
"""
FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c
STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM
IS_STUB = True
def __init__(self, rom_loader):
self.secure_download_mode = rom_loader.secure_download_mode
self._port = rom_loader._port
self._trace_enabled = rom_loader._trace_enabled
self.cache = rom_loader.cache
self.flush_input() # resets _slip_reader
ESP32C5ROM.STUB_CLASS = ESP32C5StubLoader

129
tools/python/esptool/targets/esp32c5beta3.py Normal file
View File

@@ -0,0 +1,129 @@
# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
import time
from typing import Dict
from .esp32c6 import ESP32C6ROM
from ..loader import ESPLoader
class ESP32C5BETA3ROM(ESP32C6ROM):
CHIP_NAME = "ESP32-C5(beta3)"
IMAGE_CHIP_ID = 17
IROM_MAP_START = 0x41000000
IROM_MAP_END = 0x41800000
DROM_MAP_START = 0x41000000
DROM_MAP_END = 0x41800000
# Magic value for ESP32C5(beta3)
CHIP_DETECT_MAGIC_VALUE = [0xE10D8082]
FLASH_FREQUENCY = {
"80m": 0xF,
"40m": 0x0,
"20m": 0x2,
}
MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x41800000, 0x42000000, "DROM"],
[0x40800000, 0x40880000, "DRAM"],
[0x40800000, 0x40880000, "BYTE_ACCESSIBLE"],
[0x4004A000, 0x40050000, "DROM_MASK"],
[0x40000000, 0x4004A000, "IROM_MASK"],
[0x41000000, 0x41800000, "IROM"],
[0x40800000, 0x40880000, "IRAM"],
[0x50000000, 0x50004000, "RTC_IRAM"],
[0x50000000, 0x50004000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
]
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
12: "KM_INIT_KEY",
}
def get_pkg_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 26) & 0x07
def get_minor_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
def get_major_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03
def get_chip_description(self):
chip_name = {
0: "ESP32-C5 beta3 (QFN40)",
}.get(self.get_pkg_version(), "unknown ESP32-C5 beta3")
major_rev = self.get_major_chip_version()
minor_rev = self.get_minor_chip_version()
return f"{chip_name} (revision v{major_rev}.{minor_rev})"
def get_crystal_freq(self):
# The crystal detection algorithm of ESP32/ESP8266
# works for ESP32-C5 beta3 as well.
return ESPLoader.get_crystal_freq(self)
def change_baud(self, baud):
rom_with_48M_XTAL = not self.IS_STUB and self.get_crystal_freq() == 48
if rom_with_48M_XTAL:
# The code is copied over from ESPLoader.change_baud().
# Probably this is just a temporary solution until the next chip revision.
# The ROM code thinks it uses a 40 MHz XTAL. Recompute the baud rate
# in order to trick the ROM code to set the correct baud rate for
# a 48 MHz XTAL.
false_rom_baud = baud * 40 // 48
print(f"Changing baud rate to {baud}")
self.command(
self.ESP_CHANGE_BAUDRATE, struct.pack("<II", false_rom_baud, 0)
)
print("Changed.")
self._set_port_baudrate(baud)
time.sleep(0.05) # get rid of garbage sent during baud rate change
self.flush_input()
else:
ESPLoader.change_baud(self, baud)
class ESP32C5BETA3StubLoader(ESP32C5BETA3ROM):
"""Access class for ESP32C5BETA3 stub loader, runs on top of ROM.
(Basically the same as ESP32StubLoader, but different base class.
Can possibly be made into a mixin.)
"""
FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c
STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM
IS_STUB = True
def __init__(self, rom_loader):
self.secure_download_mode = rom_loader.secure_download_mode
self._port = rom_loader._port
self._trace_enabled = rom_loader._trace_enabled
self.cache = rom_loader.cache
self.flush_input() # resets _slip_reader
ESP32C5BETA3ROM.STUB_CLASS = ESP32C5BETA3StubLoader

12
tools/python/esptool/targets/esp32c6.py
View File

@@ -6,7 +6,7 @@
import struct
from .esp32c3 import ESP32C3ROM
from util import FatalError, NotImplementedInROMError
from ..util import FatalError, NotImplementedInROMError
class ESP32C6ROM(ESP32C3ROM):
@@ -161,8 +161,10 @@ class ESP32C6ROM(ESP32C3ROM):
)
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -176,7 +178,9 @@ class ESP32C6ROM(ESP32C3ROM):
def is_flash_encryption_key_valid(self):
# Need to see an AES-128 key
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)

144
tools/python/esptool/targets/esp32c61.py Normal file
View File

@@ -0,0 +1,144 @@
# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from typing import Dict
from .esp32c6 import ESP32C6ROM
class ESP32C61ROM(ESP32C6ROM):
CHIP_NAME = "ESP32-C61"
IMAGE_CHIP_ID = 20
# Magic value for ESP32C61
CHIP_DETECT_MAGIC_VALUE = [0x33F0206F, 0x2421606F]
UART_DATE_REG_ADDR = 0x60000000 + 0x7C
EFUSE_BASE = 0x600B4800
EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
MAC_EFUSE_REG = EFUSE_BASE + 0x044
EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address
EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY0_SHIFT = 0
EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY1_SHIFT = 4
EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY2_SHIFT = 8
EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY3_SHIFT = 12
EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY4_SHIFT = 16
EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x34
EFUSE_PURPOSE_KEY5_SHIFT = 20
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x030
EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 23
EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x034
EFUSE_SECURE_BOOT_EN_MASK = 1 << 26
FLASH_FREQUENCY = {
"80m": 0xF,
"40m": 0x0,
"20m": 0x2,
}
MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x41800000, 0x42000000, "DROM"],
[0x40800000, 0x40860000, "DRAM"],
[0x40800000, 0x40860000, "BYTE_ACCESSIBLE"],
[0x4004AC00, 0x40050000, "DROM_MASK"],
[0x40000000, 0x4004AC00, "IROM_MASK"],
[0x41000000, 0x41800000, "IROM"],
[0x40800000, 0x40860000, "IRAM"],
[0x50000000, 0x50004000, "RTC_IRAM"],
[0x50000000, 0x50004000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
]
UF2_FAMILY_ID = 0x77D850C4
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
12: "KM_INIT_KEY",
13: "XTS_AES_256_KEY_1_PSRAM",
14: "XTS_AES_256_KEY_2_PSRAM",
15: "XTS_AES_128_KEY_PSRAM",
}
def get_pkg_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 26) & 0x07
def get_minor_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
def get_major_chip_version(self):
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03
def get_chip_description(self):
chip_name = {
0: "ESP32-C61",
}.get(self.get_pkg_version(), "unknown ESP32-C61")
major_rev = self.get_major_chip_version()
minor_rev = self.get_minor_chip_version()
return f"{chip_name} (revision v{major_rev}.{minor_rev})"
def get_chip_features(self):
return ["WiFi 6", "BT 5"]
def read_mac(self, mac_type="BASE_MAC"):
"""Read MAC from EFUSE region"""
mac0 = self.read_reg(self.MAC_EFUSE_REG)
mac1 = self.read_reg(self.MAC_EFUSE_REG + 4) # only bottom 16 bits are MAC
base_mac = struct.pack(">II", mac1, mac0)[2:]
# BASE MAC: 60:55:f9:f7:2c:a2
macs = {
"BASE_MAC": tuple(base_mac),
}
return macs.get(mac_type, None)
class ESP32C61StubLoader(ESP32C61ROM):
"""Access class for ESP32C61 stub loader, runs on top of ROM.
(Basically the same as ESP32StubLoader, but different base class.
Can possibly be made into a mixin.)
"""
FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c
STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM
IS_STUB = True
def __init__(self, rom_loader):
self.secure_download_mode = rom_loader.secure_download_mode
self._port = rom_loader._port
self._trace_enabled = rom_loader._trace_enabled
self.cache = rom_loader.cache
self.flush_input() # resets _slip_reader
ESP32C61ROM.STUB_CLASS = ESP32C61StubLoader

20
tools/python/esptool/targets/esp32h2.py
View File

@@ -3,8 +3,10 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
from typing import Dict
from .esp32c6 import ESP32C6ROM
from util import FatalError
from ..util import FatalError
class ESP32H2ROM(ESP32C6ROM):
@@ -32,6 +34,22 @@ class ESP32H2ROM(ESP32C6ROM):
UF2_FAMILY_ID = 0x332726F6
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
}
def get_pkg_version(self):
num_word = 4
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07

32
tools/python/esptool/targets/esp32h2beta1.py
View File

@@ -4,9 +4,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from typing import Dict
from .esp32c3 import ESP32C3ROM
from util import FatalError, NotImplementedInROMError
from ..util import FatalError, NotImplementedInROMError
from typing import List
class ESP32H2BETA1ROM(ESP32C3ROM):
@@ -66,7 +69,7 @@ class ESP32H2BETA1ROM(ESP32C3ROM):
FLASH_ENCRYPTED_WRITE_ALIGN = 16
MEMORY_MAP = []
MEMORY_MAP: List = []
FLASH_FREQUENCY = {
"48m": 0xF,
@@ -75,6 +78,21 @@ class ESP32H2BETA1ROM(ESP32C3ROM):
"12m": 0x2,
}
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "RESERVED",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
}
def get_pkg_version(self):
num_word = 4
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x07
@@ -119,8 +137,10 @@ class ESP32H2BETA1ROM(ESP32C3ROM):
return None # doesn't exist on ESP32-H2
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -134,7 +154,9 @@ class ESP32H2BETA1ROM(ESP32C3ROM):
def is_flash_encryption_key_valid(self):
# Need to see an AES-128 key
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)

59
tools/python/esptool/targets/esp32p4.py
View File

@@ -4,10 +4,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from typing import Dict
from .esp32 import ESP32ROM
from loader import ESPLoader
from util import FatalError, NotImplementedInROMError
from ..loader import ESPLoader
from ..util import FatalError, NotImplementedInROMError
class ESP32P4ROM(ESP32ROM):
@@ -21,7 +22,7 @@ class ESP32P4ROM(ESP32ROM):
BOOTLOADER_FLASH_OFFSET = 0x2000 # First 2 sectors are reserved for FE purposes
CHIP_DETECT_MAGIC_VALUE = [0x0]
CHIP_DETECT_MAGIC_VALUE = [0x0, 0x0ADDBAD0]
UART_DATE_REG_ADDR = 0x500CA000 + 0x8C
@@ -37,6 +38,8 @@ class ESP32P4ROM(ESP32ROM):
SPI_MISO_DLEN_OFFS = 0x28
SPI_W0_OFFS = 0x58
SPI_ADDR_REG_MSB = False
EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030 # BLOCK0 read base address
EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
@@ -85,17 +88,34 @@ class ESP32P4ROM(ESP32ROM):
UF2_FAMILY_ID = 0x3D308E94
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "ECDSA_KEY",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
12: "KM_INIT_KEY",
}
def get_pkg_version(self):
# ESP32P4 TODO
return 0
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 20) & 0x07
def get_minor_chip_version(self):
# ESP32P4 TODO
return 0
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
def get_major_chip_version(self):
# ESP32P4 TODO
return 0
num_word = 2
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 4) & 0x03
def get_chip_description(self):
chip_name = {
@@ -112,6 +132,9 @@ class ESP32P4ROM(ESP32ROM):
# ESP32P4 XTAL is fixed to 40MHz
return 40
def get_flash_voltage(self):
pass # not supported on ESP32-P4
def override_vddsdio(self, new_voltage):
raise NotImplementedInROMError(
"VDD_SDIO overrides are not supported for ESP32-P4"
@@ -136,8 +159,10 @@ class ESP32P4ROM(ESP32ROM):
)
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -151,7 +176,9 @@ class ESP32P4ROM(ESP32ROM):
def is_flash_encryption_key_valid(self):
# Need to see either an AES-128 key or two AES-256 keys
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
return True
@@ -170,7 +197,13 @@ class ESP32P4ROM(ESP32ROM):
# self.disable_watchdogs()
def check_spi_connection(self, spi_connection):
pass # TODO: Define GPIOs for --spi-connection
if not set(spi_connection).issubset(set(range(0, 55))):
raise FatalError("SPI Pin numbers must be in the range 0-54.")
if any([v for v in spi_connection if v in [24, 25]]):
print(
"WARNING: GPIO pins 24 and 25 are used by USB-Serial/JTAG, "
"consider using other pins for SPI flash connection."
)
class ESP32P4StubLoader(ESP32P4ROM):

57
tools/python/esptool/targets/esp32s2.py
View File

@@ -5,11 +5,12 @@
import os
import struct
from typing import Dict
from .esp32 import ESP32ROM
from loader import ESPLoader
from reset import HardReset
from util import FatalError, NotImplementedInROMError
from ..loader import ESPLoader
from ..reset import HardReset
from ..util import FatalError, NotImplementedInROMError
class ESP32S2ROM(ESP32ROM):
@@ -31,6 +32,8 @@ class ESP32S2ROM(ESP32ROM):
SPI_MISO_DLEN_OFFS = 0x28
SPI_W0_OFFS = 0x58
SPI_ADDR_REG_MSB = False
MAC_EFUSE_REG = 0x3F41A044 # ESP32-S2 has special block for MAC efuses
UART_CLKDIV_REG = 0x3F400014
@@ -81,6 +84,7 @@ class ESP32S2ROM(ESP32ROM):
GPIO_STRAP_REG = 0x3F404038
GPIO_STRAP_SPI_BOOT_MASK = 0x8 # Not download mode
GPIO_STRAP_VDDSPI_MASK = 1 << 4
RTC_CNTL_OPTION1_REG = 0x3F408128
RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1 # Is download mode forced over USB?
@@ -99,8 +103,29 @@ class ESP32S2ROM(ESP32ROM):
[0x50000000, 0x50002000, "RTC_DATA"],
]
EFUSE_VDD_SPI_REG = EFUSE_BASE + 0x34
VDD_SPI_XPD = 1 << 4
VDD_SPI_TIEH = 1 << 5
VDD_SPI_FORCE = 1 << 6
UF2_FAMILY_ID = 0xBFDD4EEE
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "RESERVED",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
}
def get_pkg_version(self):
num_word = 4
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
@@ -183,6 +208,9 @@ class ESP32S2ROM(ESP32ROM):
# ESP32-S2 XTAL is fixed to 40MHz
return 40
def _get_rtc_cntl_flash_voltage(self):
return None # not supported on ESP32-S2
def override_vddsdio(self, new_voltage):
raise NotImplementedInROMError(
"VDD_SDIO overrides are not supported for ESP32-S2"
@@ -215,8 +243,10 @@ class ESP32S2ROM(ESP32ROM):
)
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -230,7 +260,9 @@ class ESP32S2ROM(ESP32ROM):
def is_flash_encryption_key_valid(self):
# Need to see either an AES-128 key or two AES-256 keys
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
return True
@@ -266,15 +298,12 @@ class ESP32S2ROM(ESP32ROM):
strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0
and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
):
print(
"WARNING: {} chip was placed into download mode using GPIO0.\n"
"esptool.py can not exit the download mode over USB. "
"To run the app, reset the chip manually.\n"
"To suppress this note, set --after option to 'no_reset'.".format(
self.get_chip_description()
)
raise SystemExit(
f"Error: {self.get_chip_description()} chip was placed into download "
"mode using GPIO0.\nesptool.py can not exit the download mode over "
"USB. To run the app, reset the chip manually.\n"
"To suppress this note, set --after option to 'no_reset'."
)
raise SystemExit(1)
def hard_reset(self):
uses_usb_otg = self.uses_usb_otg()

67
tools/python/esptool/targets/esp32s3.py
View File

@@ -5,11 +5,12 @@
import os
import struct
from typing import Dict
from .esp32 import ESP32ROM
from loader import ESPLoader
from reset import HardReset
from util import FatalError, NotImplementedInROMError
from ..loader import ESPLoader
from ..reset import HardReset
from ..util import FatalError, NotImplementedInROMError
class ESP32S3ROM(ESP32ROM):
@@ -34,6 +35,8 @@ class ESP32S3ROM(ESP32ROM):
SPI_MISO_DLEN_OFFS = 0x28
SPI_W0_OFFS = 0x58
SPI_ADDR_REG_MSB = False
BOOTLOADER_FLASH_OFFSET = 0x0
SUPPORTS_ENCRYPTED_FLASH = True
@@ -95,6 +98,7 @@ class ESP32S3ROM(ESP32ROM):
GPIO_STRAP_REG = 0x60004038
GPIO_STRAP_SPI_BOOT_MASK = 0x8 # Not download mode
GPIO_STRAP_VDDSPI_MASK = 1 << 4
RTC_CNTL_OPTION1_REG = 0x6000812C
RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1 # Is download mode forced over USB?
@@ -115,8 +119,29 @@ class ESP32S3ROM(ESP32ROM):
[0x50000000, 0x50002000, "RTC_DATA"],
]
EFUSE_VDD_SPI_REG = EFUSE_BASE + 0x34
VDD_SPI_XPD = 1 << 4
VDD_SPI_TIEH = 1 << 5
VDD_SPI_FORCE = 1 << 6
UF2_FAMILY_ID = 0xC47E5767
EFUSE_MAX_KEY = 5
KEY_PURPOSES: Dict[int, str] = {
0: "USER/EMPTY",
1: "RESERVED",
2: "XTS_AES_256_KEY_1",
3: "XTS_AES_256_KEY_2",
4: "XTS_AES_128_KEY",
5: "HMAC_DOWN_ALL",
6: "HMAC_DOWN_JTAG",
7: "HMAC_DOWN_DIGITAL_SIGNATURE",
8: "HMAC_UP",
9: "SECURE_BOOT_DIGEST0",
10: "SECURE_BOOT_DIGEST1",
11: "SECURE_BOOT_DIGEST2",
}
def get_pkg_version(self):
num_word = 3
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07
@@ -221,8 +246,10 @@ class ESP32S3ROM(ESP32ROM):
return None # doesn't exist on ESP32-S3
def get_key_block_purpose(self, key_block):
if key_block < 0 or key_block > 5:
raise FatalError("Valid key block numbers must be in range 0-5")
if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
raise FatalError(
f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
)
reg, shift = [
(self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -236,7 +263,9 @@ class ESP32S3ROM(ESP32ROM):
def is_flash_encryption_key_valid(self):
# Need to see either an AES-128 key or two AES-256 keys
purposes = [self.get_key_block_purpose(b) for b in range(6)]
purposes = [
self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
]
if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
return True
@@ -251,6 +280,9 @@ class ESP32S3ROM(ESP32ROM):
& self.EFUSE_SECURE_BOOT_EN_MASK
)
def _get_rtc_cntl_flash_voltage(self):
return None # not supported on ESP32-S3
def override_vddsdio(self, new_voltage):
raise NotImplementedInROMError(
"VDD_SDIO overrides are not supported for ESP32-S3"
@@ -328,21 +360,28 @@ class ESP32S3ROM(ESP32ROM):
strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0
and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
):
print(
"WARNING: {} chip was placed into download mode using GPIO0.\n"
"esptool.py can not exit the download mode over USB. "
"To run the app, reset the chip manually.\n"
"To suppress this note, set --after option to 'no_reset'.".format(
self.get_chip_description()
)
raise SystemExit(
f"Error: {self.get_chip_description()} chip was placed into download "
"mode using GPIO0.\nesptool.py can not exit the download mode over "
"USB. To run the app, reset the chip manually.\n"
"To suppress this note, set --after option to 'no_reset'."
)
raise SystemExit(1)
def hard_reset(self):
uses_usb_otg = self.uses_usb_otg()
if uses_usb_otg:
self._check_if_can_reset()
try:
# Clear force download boot mode to avoid the chip being stuck in download mode after reset
# workaround for issue: https://github.com/espressif/arduino-esp32/issues/6762
self.write_reg(
self.RTC_CNTL_OPTION1_REG, 0, self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK
)
except Exception:
# Skip if response was not valid and proceed to reset; e.g. when monitoring while resetting
pass
print("Hard resetting via RTS pin...")
HardReset(self._port, uses_usb_otg)()

10
tools/python/esptool/targets/esp8266.py
View File

@@ -3,8 +3,8 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
from loader import ESPLoader
from util import FatalError, NotSupportedError
from ..loader import ESPLoader
from ..util import FatalError, NotSupportedError
class ESP8266ROM(ESPLoader):
@@ -169,12 +169,18 @@ class ESP8266ROM(ESPLoader):
else:
return (num_sectors - head_sectors) * sector_size
def get_flash_voltage(self):
pass # not supported on ESP8266
def override_vddsdio(self, new_voltage):
raise NotSupportedError(self, "Overriding VDDSDIO")
def check_spi_connection(self, spi_connection):
raise NotSupportedError(self, "Setting --spi-connection")
def get_secure_boot_enabled(self):
return False # ESP8266 doesn't have security features
class ESP8266StubLoader(ESP8266ROM):
"""Access class for ESP8266 stub loader, runs on top of ROM."""

3
tools/python/esptool/targets/stub_flasher/1/README.md Normal file
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@@ -0,0 +1,3 @@
# Licensing
The binaries in JSON format distributed in this directory are released as Free Software under GNU General Public License Version 2 or later. They were released at https://github.com/espressif/esptool-legacy-flasher-stub/releases/tag/v1.3.0 from where the sources can be obtained.

0
tools/python/esptool/targets/stub_flasher/stub_flasher_32.json → tools/python/esptool/targets/stub_flasher/1/esp32.json
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tools/python/esptool/targets/stub_flasher/stub_flasher_32c2.json → tools/python/esptool/targets/stub_flasher/1/esp32c2.json
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tools/python/esptool/targets/stub_flasher/1/esp32c3.json Normal file
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tools/python/esptool/targets/stub_flasher/1/esp32c5.json Normal file
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tools/python/esptool/targets/stub_flasher/1/esp32c5beta3.json Normal file
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@@ -0,0 +1,8 @@
{
"entry": 1082131910,
"text": "ARG3BwBgTsaDqYcASsg3CYRAJspSxAbOIsy3BABgfVoTCQkAwEwTdPQ/DeDyQGJEI6g0AUJJ0kSySSJKBWGCgIhAgycJABN19Q+Cl30U4xlE/8m/EwcADJRBqodjGOUAhUeFxiOgBQB5VYKABUdjh+YACUZjjcYAfVWCgEIFEwewDUGFY5XnAolHnMH1t5MGwA1jFtUAmMETBQAMgoCTBtANfVVjldcAmMETBbANgoC3NYVAQRGThQW6BsZhP2NFBQa3N4VAk4eHsQOnBwgD1kcIE3X1D5MGFgDCBsGCI5LXCDKXIwCnAAPXRwiRZ5OHBwRjHvcCN7eEQBMHh7GhZ7qXA6YHCLf2hEC3N4VAk4eHsZOGhrVjH+YAI6bHCCOg1wgjkgcIIaD5V+MG9fyyQEEBgoAjptcII6DnCN23NzcAYHxLnYv1/zcnAGB8S52L9f+CgEERBsbdN7c3AGAjpgcCNwcACJjDmEN9/8hXskATRfX/BYlBAYKAQREGxtk/fd03BwBAtzcAYJjDNzcAYBxD/f+yQEEBgoBBESLEN4SEQJMHxABKwAOpBwEGxibCYwoJBEU3OcW9RxMExACBRGPWJwEERL2Ik7QUAH03hT8cRDcGgAATl8cAmeA3BgABt/b/AHWPtzYAYNjCkMKYQn3/QUeR4AVHMwnpQLqXIygkARzEskAiRJJEAklBAYKAQREGxhMHAAxjEOUCEwWwDZcAgP/ngIDjEwXADbJAQQEXA4D/ZwCD4hMHsA3jGOX+lwCA/+eAgOETBdANxbdBESLEJsIGxiqEswS1AGMXlACyQCJEkkRBAYKAA0UEAAUERTfttxMFAAwXA4D/ZwAD3jVxJstOx/1yhWn9dCLNSslSxVbDBs+ThIT6FpGThwkHppcYCLOE5wAqiSaFLoSXAID/54DgSJOHCQcYCAVqupezikdBMeQFZ311kwWF+pMHBwcTBYX5FAiqlzOF1wCTBwcHrpezhdcAKsaXAID/54CgRTJFwUWhPwFFhWIWkfpAakTaREpJukkqSppKDWGCgKKJY3OKAIVpTobWhUqFlwCA/+eA4OITdfUPAe1OhtaFJoWXAID/54DgQE6ZMwQ0QVG3EwUwBlW/MXH9ck7XUtVW017PBt8i3SbbStla0WLNZstqyW7HqokWkRMFAAIuirKKtosCypcAgP/ngKA7hWdj4FcThWR9dBMEhPqThwQHopcYCDOE5wAihZcAgP/ngCA6fXsTDDv5kwyL+ROHBAeThwQHFAhil+aXAUkzDNcAs4zXAFJNY3xNCWNxqQNBqFU1poUIAaU9cT0mhgwBIoWXAID/54AANqaZJpljdUkDswepQWPxdwOzBCpBY/OaANaEJoYMAU6FlwCA/+eAQNQTdfUPVd0CzIFEeV2NTaMJAQBihZcAgP/ngMDDffkDRTEB5oUFMWNPBQDj4p3+hWeThwcHppcYCLqX2pcjiqf4hQTxt+MVpf2RR+OF9PYFZ311kwcHB5MFhfoTBYX5FAiqlzOF1wCTBwcHrpezhdcAKsaXAID/54AgLO0zMkXBRX07zTMTBQAClwCA/+eAwCmFYhaR+lBqVNpUSlm6WSpamloKW/pLakzaTEpNuk0pYYKAAREGziLMnTk3BM4/bAATBUT/lwCA/+eAwMqqhwVFleeyR5P3ByA+xkE5NzcAYBxHtwZAABMFRP/VjxzHskWXAID/54BAyDM1oADyQGJEBWGCgEERt4eEQAbGk4fHAAVHI4DnABPXxQCYxwVnfRfMw8jH+Y06laqVsYGMyyOqBwBBNxnBEwVQDLJAQQGCgAERIsw3hIRAkwfEACbKxEdOxgbOSsiqiRMExABj85UAroSpwAMpRAAmmRNZyQAcSGNV8AAcRGNe+QLpNn3dSEAmhs6FlwCA/+eAQLsTdfUPAcWTB0AMXMhcQKaXXMBcRIWPXMTyQGJE0kRCSbJJBWGCgOE+bb+3V0FJGXGTh/eEAUU+zobeotym2srYztbS1NbS2tDezuLM5srqyO7GlwCA/+eAoK23B4RANzeFQJOHBwATB4e6Y+DnFK0xkUVoCD05jTG3t4RAk4eHsSFnPpcjIPcItwWAQLcHgEABRpOHBwuThQUANwmEQBVFIyD5AJcAgP/ngMAONwcAYFxHEwUAAreEhECT5xcQXMeXAID/54CADbcXCWCIX4FFtzmFQHGJYRUTNRUAlwCA/+eAQLbBZ/0XEwcAEIVmQWa3BQABAUWThMQAtwqEQA1qlwCA/+eAAKyTiYmxEwkJABOLygAmmoOnyQj134OryQiFRyOmCQgjAvECg8cbAAlHIxPhAqMC8QIC1E1HY4vnBlFHY4nnBilHY5/nAIPHOwADxysAogfZjxFHY5bnAIOniwCcQz7UjT6hRUgQmTaDxzsAA8crAKIH2Y8RZ0EHY373AhMFsA2XAID/54BgkxMFwA2XAID/54CgkhMF4A6XAID/54DgkQ0+vbcjoAcAkQdtvclHIxPxAn23A8cbANFGY+fmAoVGY+bmAAFMEwTwD52oeRcTd/cPyUbj6Ob+tzaFQAoHk4bGujaXGEMCh5MGBwOT9vYPEUbjadb8Ewf3AhN39w+NRmPu5gi3NoVACgeThoa/NpcYQwKHEwdAAmOa5xAC1B1EAUWXAID/54BAiQFFiTRVNE00oUVIEH0UlTx98AFMAUQTdfQPLTQTdfwPFTRZNOMRBOyDxxsASUdjZfcwCUfjeffq9ReT9/cPPUfjY/fqNzeFQIoHEweHwLqXnEOChwVEnetwEIFFAUWXAID/54BgiR3h0UVoEBk8AUQxqAVEge+XAID/54DgjTM0oAApoCFHY4XnAAVEAUxhtwOsiwADpMsAs2eMANIH9feZOWX1wWwinP0cfX0zBYxAXdyzd5UBlePBbDMFjEBj5owC/XwzBYxAXdAxgZcAgP/ngICKXflmlPW3MYGXAID/54CAiV3xapTRt0GBlwCA/+eAwIhZ+TMElEHBtyFH44rn8AFMEwQADDm3QUfNv0FHBUTjnef2g6XLAAOliwBZOrm/QUcFROOT5/YDpwsBkWdj6Oceg6VLAQOliwAxMYG3QUcFROOU5/SDpwsBEWdjafccA6fLAIOlSwEDpYsAM4TnAt02I6wEACMkirAJvwPHBABjAwcUA6eLAMEXEwQADGMT9wDASAFHkwbwDmNG9wKDx1sAA8dLAAFMogfZjwPHawBCB12Pg8d7AOIH2Y/jhPbmEwQQDIW1M4brAANGhgEFB7GO4beDxwQA/cfcRGOdBxTASCOABABVvWFHY5bnAoOnywEDp4sBg6ZLAQOmCwGDpcsAA6WLAJfwf//ngIB5KowzNKAAAb0BTAVEKbURRwVE453n5reXAGC0X2V3fRcFZvmO0Y4DpYsAtN+0V4FF+Y7RjrTX9F/5jtGO9N/0U3WPUY/405fwf//ngKB8BbUT9/cA4xcH6pPcRwAThIsAAUx9XeN3nNtIRJfwf//ngGBgGERUQBBA+Y5jB6cBHEITR/f/fY/ZjhTCBQxBBNm/EUe1tUFHBUTjmufeg6eLAAOnSwEjJPkAIyLpAMmzgyVJAMEXkeWJzwFMEwRgDKG7AyeJAGNm9wYT9zcA4xsH4gMoiQABRgFHMwXoQLOG5QBjafcA4wcG0iMkqQAjItkADbMzhusAEE4RB5DCBUbpvyFHBUTjlOfYAySJABnAEwSADCMkCQAjIgkAMzSAAL2zAUwTBCAMxbkBTBMEgAzlsQFMEwSQDMWxEwcgDWOD5wwTB0AN45HnugPEOwCDxysAIgRdjJfwf//ngIBfA6zEAEEUY3OEASKM4w8MtsBAYpQxgJxIY1XwAJxEY1r0Cu/wr+B13chAYoaThYsBl/B//+eAgFsBxZMHQAzcyNxA4pfcwNxEs4eHQdzEl/B//+eAYFoVvgllEwUFcQOsywADpIsAl/B//+eA4Eq3BwBg2Eu3BgABwRaTV0cBEgd1j72L2Y+zh4cDAUWz1YcCl/B//+eAQEwTBYA+l/B//+eAgEfdtIOmSwEDpgsBg6XLAAOliwDv8K/2wbyDxTsAg8crABOFiwGiBd2NwRWpOm287/AP2oG3A8Q7AIPHKwATjIsBIgRdjNxEQRTF45FHhUtj/ocIkweQDNzIebQDpw0AItAFSLOH7EA+1oMnirBjc/QADUhCxjrE7/CP1SJHMkg3hYRA4oV8EJOGygAQEBMFRQKX8H//54AASje3hECTCMcAglcDp4iwg6UNAB2MHY8+nLJXI6TosKqLvpUjoL0Ak4fKAJ2NAcWhZ2OW9QBahV04I6BtAQnE3ESZw+NAcPlj3wsAkwdwDIW/hUu3PYVAt4yEQJONjbqTjMwA6b/jlQue3ETjggeekweADLG3g6eLAOObB5wBRZfwf//ngCA5CWUTBQVxl/B//+eAwDSX8H//54DAOU26A6TLAOMGBJoBRZfwf//ngIA2EwWAPpfwf//ngEAyApRBuvZQZlTWVEZZtlkmWpZaBlv2S2ZM1kxGTbZNCWGCgAAA",
"text_start": 1082130432,
"data": "DACEQO4IgEA6CYBAkgmAQGAKgEDMCoBAegqAQLYHgEAcCoBAXAqAQKYJgEBmB4BA2gmAQGYHgEDICIBADAmAQDoJgECSCYBA2giAQCAIgEBQCIBA1giAQCQNgEA6CYBA5AuAQNgMgECyBoBAAg2AQLIGgECyBoBAsgaAQLIGgECyBoBAsgaAQLIGgECyBoBAgAuAQLIGgEAADIBA2AyAQA==",
"data_start": 1082469288,
"bss_start": 1082392576
}

8
tools/python/esptool/targets/stub_flasher/1/esp32c6.json Normal file
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tools/python/esptool/targets/stub_flasher/1/esp32c61.json Normal file
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tools/python/esptool/targets/stub_flasher/stub_flasher_32c6beta.json → tools/python/esptool/targets/stub_flasher/1/esp32c6beta.json
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tools/python/esptool/targets/stub_flasher/1/esp32h2.json Normal file
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tools/python/esptool/targets/stub_flasher/stub_flasher_32h2beta1.json → tools/python/esptool/targets/stub_flasher/1/esp32h2beta1.json
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0
tools/python/esptool/targets/stub_flasher/stub_flasher_32h2beta2.json → tools/python/esptool/targets/stub_flasher/1/esp32h2beta2.json
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8
tools/python/esptool/targets/stub_flasher/1/esp32p4.json Normal file
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@@ -0,0 +1,8 @@
{
"entry": 1341195918,
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# Licensing
The binaries in JSON format distributed in this directory are dual licensed under the Apache License Version 2.0 or the MIT license. They were released at https://github.com/esp-rs/esp-flasher-stub/releases/tag/v0.3.0 from where the sources can be obtained.

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